fhlow is a framework written in Ruby that handles the design-flow of the digital hardware design process for VHDL desings for FPGAs and is (of course) avaliable under the GPL for Microsoft Windows and GNU/Linux Systems.
The engineer should be able to concentrate on his actual work (the source code and the architecture of the chip) and shouldn't have to waste time in configuring programs or structuring the work. A couple of hierachical config-files handle all settings for simulation, synthesis, place and route and the specific hardware.

fhlow was part of a students project at Upper Austria University of Applied Sciences department HSSE in Hagenberg called esther . The achievment of the complete redesign during my diploma thesis will be published on this site which will include documentation (for users and developers), and downloads (the actual fhlow scripts and plugins).
You will also find a wiki, a forum and a bugtracker for sharing your experiences, howtos, featrure requests and bugs ;).